1. Field of the Invention
The present invention relates to circuits for the simultaneous transmission and reception of signals (“full duplex” communications) over a transmission line, and especially circuits of this type including an echo canceller.
2. Discussion of the Related Art
Commonly-called “full-duplex” communications (simultaneous transmission and reception of signals) can be of two different types. In a first type, the signals are transmitted and received over different frequency ranges and, in a second type, they are transmitted and received over the same frequency range.
When the transmitted and received signals are in the same frequency range, the transmitted and received signals are superposed in the reception channel and an “echo canceller” is necessary to subtract from the received signals the fraction of the transmitted signals that is present on the receive side.
FIG. 1 shows a conventional circuit 2 including such an echo canceller. Circuit 2 is provided for exchanging signals with an exchange 4 via a two-wire transmission line 6. Circuit 2 includes a digital transmit block 8 and a digital receive block 10. Block 8 can receive signals to be transmitted from a microprocessor (not shown) and block 10 can provide the microprocessor with the received signals for processing. Circuit 2 then behaves as a modem. A digital-to-analog converter (DAC) 12 converts the digital signal provided by transmit block 8 into an analog output signal A. An analog-to-digital converter (ADC) 14 converts analog signal R corresponding to the received signal into a digital signal supplied to receive block 10.
An analog unit 16 is arranged between the output of converter 12, the input of converter 14, and a terminal 17 connected to one end of a primary winding of an isolation transformer 18. The other end of the primary winding of transformer 18 is grounded, and each end of the secondary winding of transformer 18 is connected to a wire of line 6. Unit 16 includes a resistor R1 connected between the output of converter 12 and terminal 17. Unit 16 also includes a voltage divider formed of two resistors R2 and R3 connected in series between the output of converter 12 and the ground. An analog subtractor 19 is connected to subtract the signal provided by the voltage divider from the signal present on terminal 17. The output of subtractor 19 is connected to the input of converter 14.
The value of resistor R1 is equal to the line impedance, as seen from the primary of transformer 18. Accordingly, signal A being provided by converter 12, a signal A/2 is present on terminal 17. Further, the values of resistors R2 and R3 are equal and the voltage divider provides a signal A/2 at its midpoint. When a signal B is provided by exchange 4, a signal A/2+B is present on terminal 17 and, at the output of subtractor 19, the signal is: R=A/2+B−A/2, that is, B. Thereby, signal R provided to converter 14 contains no disturbances from transmitted signal A.
In practice, it is difficult to perfectly adjust resistance R1 to the line impedance, which can by the way include a reactive component. Circuit 10 then receives a so-called “close echo” signal. This close echo is due to a fraction of signal A that is present in signal R without having crossed the transmission line. The circuit also receives a fainter so-called “remote echo” signal, due to the reflection of the transmitted signal at the end of the transmission line. The present invention does not deal with the remote echo signal, and “echo” will hereafter only designate the close echo.
When there is an echo AA, signal R is equal to B+ΔA. To suppress echo signal ΔA, circuit 2 includes a digital echo canceller coupled between the output of block 8, the output of converter 14, and the input of block 10. The echo canceller includes a digital filter 20 for generating a signal representative of the echo and a digital subtractor 22 for subtracting this signal representative of the echo from the digital signal generated by converter 14.
FIG. 2 schematically shows a conventional filter 20. Filter 20 includes a predetermined number N of series-connected delay elements 26i, where i is included between 1 and N. The first element 261 receives as an input the samples corresponding to the digital signal provided by block 8. Elements 26i each introduce a delay equal to the sampling period T of the transmitted signal. For each new sample D0 received as an input by element 261, elements 26i each provide a sample Di respectively delayed by i periods with respect to sample D0. Filter 20 also includes N multipliers 28i. Each multiplier 28i is provided for multiplying one of delayed elements Di by a coefficient Ki. Filter 20 includes an adder 30 that sums up the products Ki.Di. Adder 30 provides the output signal of filter 20, designated as E, corresponding to an estimate of the echo. Coefficients Ki are generated by a calculation means, not shown for reasons of clarity.
At the beginning of each communication, an initialization phase takes place. In this initialization phase, exchange 4 transmits no signal, block 8 transmits signal A, and signal R is equal to ΔA only. Each coefficient Ki, null at the beginning of the initialization phase, is iteratively calculated by means of the following equation:Ki(t)=Ki(t−1)+ε.Err(t).Di(t)  (1)
Two successive iterations are separated by an integral number of periods T. Ki(t) and Ki(t−1) respectively are the value of coefficient Ki at time t of the iteration and upon the preceding iteration, ε is a predetermined attenuation factor, Err(t) and Di(t) respectively are the output signal of subtractor 22 and sample Di at time t of the iteration. Signal Err(t) can be positive or negative. In the initialization, the value of coefficients Ki varies until signal Err(t) is substantially null. The values of coefficients Ki then almost no longer vary and are stored in a memory (not shown).
After the initialization phase, the signal exchange starts and the exchange transmits a signal B; converter 14 receives an analog signal R equal to B+ΔA that it provides, in a digitized form, to subtractor 22. Filter 20 provides signal E corresponding to ΔA and block 10 receives an echo-free digital signal.
A disadvantage of such a device is that the values of coefficients Ki are set during the entire communication and correspond to the operating conditions of circuit 2 during the initialization phase. Now, during circuit operation, the operating conditions may change, and the estimated echo signal E may no longer be equal to the real echo signal. For example, in operation, the circuit temperature increases and the transformer's impedance may change. Such a phenomenon currently occurs when the initialization phase takes place immediately after circuit powering-on, and the temperature of circuit 2 and of transformer 18 increases after the initialization phase. The echo, which is poorly compensated for, then disturbs the receive signal and can make it impossible to use.
A solution then consists of interrupting the ongoing communication and of initiating a new communication. This enables new calculation of coefficients Kj in a new initialization phase. However, this “brutal” solution is sometimes extremely inconvenient. In the case of an Internet communication, for example, such an interruption can cause a loss of connection.